1. Field of the Invention
The present invention relates to the field of testing and debugging computer systems, in particular, microprocessor based computer systems. More specifically, the present invention relates to testing and debugging using in-circuit emulation.
2. Art Background
Microprocessor based computer systems are well known and widely available. Generally, the heart of a microprocessor system is a single integrated circuit (IC) chip which contains a processor. Typically, after going through a boot-strap initialization process, the processor reads, decodes and executes a stream of instructions which together form a program or process. Usually, the process is stored in random access memory (RAM) or read only memory (ROM) which is external to the processor chip.
Frequently, when a process is being executed by the processor, a hardware interrupt will occur which causes the processor to suspend execution of the first process and initiate a second process in response to the hardware interrupt. Later, when the second process completes, the processor will return to executing the first process. Additionally, multi-tasking processors are becoming more common. In a multi-tasking processor, a time division multiplexing scheme is implemented by the processor so that the processor appears to be executing several separate processes concurrently. In actuality, the processor is rapidly cycling among several processes and executing a small part of a given process before moving on to execute a small part of the next process in the sequence.
Prototype hardware and system software for a microprocessor system are often tested and debugged using a secondary auxiliary processor (host system), which monitors and controls the prototype system under test (target system). The host system is also known as an in-circuit emulator or development system. Additionally, if the operating software of the target system is not functional enough to permit a local debugger to execute on the target system, testing and debugging are performed using a remote debugger on the host system.
In order for the host system to be able to monitor and control the target system, the host system must be able to stop the target system, inspect or modify the processor and system state, and then allow the target system to resume normal operation. More specifically, the host system typically will be able to:
a) stop the processor of the target system PA1 b) inspect the registers and memory locations of the target system, to determine the state of the target system, PA1 c) provide a command or instruction to the processor of the target system for execution, PA1 d) modify the registers and memory locations of the target system, PA1 e) alter the program counters of the target system to resume program execution on the target system at a different location than the location the target system relinquished control to the host system, and PA1 f) cause the target system to resume normal operation.
Traditionally, additional pins are provided to the pin-out of the processor chip or a special version of the processor chip of the target system, to allow the host system to be connected to the target system and to perform the monitor and control functions described above. The host system stops the target system by asserting a break signal on one or more of the additional pins of the processor chip. Upon receiving the break signal, the processor chip generally completes the instruction which it is currently executing and then stops and awaits further instructions from the host system. There is frequently a delay from the time that the break is asserted by the host system until the target system stops execution. Additionally, it is not always possible for the host system to observe the state of the target and send the break signal at the proper time to stop the target system at a desired point of execution.